1. Field
Example embodiments relate to a semiconductor memory device, and more particularly, to a phase-change random access memory (PRAM) device including main word lines and sub-word lines connected to the main word lines, the main word lines and the sub-word lines being disposed in different layers, wherein each sub-word line (or each local word line) has the same number of jump contacts for connecting the main word lines (or global word lines) to a transistor of a sub-word line decoder, or the main word lines are bent several times so that a parasitic resistance on a word line may be reduced, a sensing margin may be increased, and power consumption may be reduced.
2. Description of the Related Art
A phase-change random access memory (PRAM) device is a type of non-volatile memory in which data is stored by using a material, e.g., germanium, antimony, and tellurium (GeSbTe), also referred to as GST, of which resistance changes according to a phase change corresponding to a temperature change (hereinafter, referred to as a phase-change material). The PRAM device has non-volatile and relatively low power consumption characteristics and includes all advantages of a dynamic random access memory (DRAM), thereby considered to be the next-generation memory.
FIG. 1 is an equivalent circuit diagram of a unit cell C of a conventional PRAM device. FIG. 2 is a cross-sectional view of a memory device ME including the phase-change material GST shown in FIG. 1. Referring to FIGS. 1 and 2, the PRAM device includes the memory device ME and a P-N diode (D) in a unit cell C. The phase-change material GST is connected to a bit line BL, which is connected to a p-junction of a diode D, and a word line WL, which is connected to an N-junction of the diode D. The PRAM device may include a transistor (not shown) which is connected to the phase-change material GST (not to the diode D illustrated in FIG. 1).
The memory device ME includes the phase-change material GST. The phase-change material GST is in a crystalline or amorphous state in the unit cell C of the PRAM device according to temperature and heating time so that information may be stored in the unit cell C of the PRAM device. A relatively high temperature above 900° C. is required for phase-change of the phase-change material GST, obtained by Joule heating in response to a current that flows through a phase-change memory cell.
When the current is supplied to a lower electrode BEC of the memory device ME, the volume and state of PGM, which is a contact portion between the phase-change material GST and the lower electrode BEC, is changed according to the current. A change in PGM allows the crystalline state of the phase-change material GST to be determined.
FIG. 3 is a graph showing time (in seconds) versus temperature (TMP), which represents the characteristic of the phase-change material GST of FIGS. 1 and 2. Reference numeral “CON1” of FIG. 3 represents a condition on which the phase-change material GST is in an amorphous state, and reference numeral “CON0” of FIG. 3 represents a condition on which the phase-change material GST is in a crystalline state. A write operation and a read operation in the PRAM device will be described with reference to FIGS. 1 through 3.
First, the write operation will be described. When the phase-change material GST is rapidly cooled after the phase-change material GST is heated to above a melting temperature TMP2 (t1), the phase-change material GST enters an amorphous state. Such an amorphous state is defined as information “1”. This state is also called a reset state. In order to store information “0”, the phase-change material GST is slowly cooled after the phase-change material GST is heated to above a crystallization temperature TMP1 and is kept at that temperature for a predetermined or given amount of time (t2). In this case, the phase-change material GST enters a crystalline state. Such a crystalline state is defined as information “0”. This state is also called a set state.
The read operation will be described. A memory cell C to be read is selected by selecting a bit line BL and a word line WL, which correspond to each other. A read current is supplied to the selected memory cell C, and values “1” and “0” are discriminated as a difference in a voltage change due to a resistance state of the phase-change material GST.
However, when a write or read operation into or from the selected memory cell C is performed, and a parasitic resistance R illustrated in FIG. 1 exists in the word line WL, a sensing margin may be reduced or a cell current required for a write or read operation may be increased. The parasitic resistance R that exists in the word line WL may depend on several factors. Hereinafter, an increase in a word line resistance due to jump contacts between a main word line and a sub-word line driver, which is one factor for increasing word line resistance, will be described.
FIG. 4 illustrates a PRAM device in which main word lines and sub-word lines are disposed on the same layer. Referring to FIG. 4, main word lines MWL0 and MWL1 are disposed on the same layer on which eight sub-word lines SWL0 to SWL7 and SWL8 to SWL15, corresponding to one another, are disposed. Thus, data cannot be stored in memory cells of an area ARE1 in which the main word lines MWL0 and MWL1 are disposed. In other words, cells that exist in the area ARE1 in which the main word lines MWL0 and MWL1 are disposed become dummy cells.